Design & Verification2026
AXI4-Stream Packet FIFO
Store-and-forward RTL with a UVM environment that predicts every drop exactly
- SystemVerilog
- UVM 1.2
- AXI4-Stream
- Questa
- Verilator
- SVA
- Functional coverage
A store-and-forward packet FIFO that sits upstream of a network MAC and buffers whole frames so the MAC never underruns when the source stalls mid-packet. The design is built around a three-pointer commit/rewind scheme, and the UVM environment verifies it against a timing-independent contract rather than a cycle-by-cycle occupancy mirror.
- 01
Three-pointer commit and rewind
wr_ptr advances speculatively on every accepted beat, wr_ptr_commit marks the end of the last whole packet and doubles as the rewind target, and rd_ptr only ever sees committed packets. A dropped frame costs one pointer assignment.
- 02
Drop-on-overflow without deadlock
A packet is dropped only when the entire buffer holds a single in-progress packet, so anything that fits is never dropped. Once dropping starts the FIFO holds tready high and sinks the rest of the doomed frame to tlast, so the AXI4-Stream master never locks up.
- 03
Exact scoreboarding from a design contract
Because the drop rule collapses to length > DEPTH always drops and length <= DEPTH never drops, the scoreboard predicts drops deterministically instead of racing the DUT's internal occupancy. That removes the false-failure problem that plagues cycle-accurate monitors.
- 04
Configurable slave-side backpressure VIP
A new axi4_stream_slave_driver generates tready under four policies — always ready, random, stall, and blocked — layered onto Greg Stitt's parameterized AXI4-Stream agent, which is reused unchanged.
- 05
Mutation-tested checkers
Five bugs were deliberately injected — overeager drop, commit pointer off-by-one, missing rewind, stall-during-drop, and plain FIFO instead of store-and-forward. All five were caught by the assertions and scoreboard, proving the checkers actually check.
