FPGA / Acceleration2026
DE10-Nano OpenCL Acceleration
Standing up an ARM-to-FPGA OpenCL platform from BSP to running kernels
- OpenCL
- C++
- Quartus Prime 18.1
- Qsys
- Cyclone V
- ARM Cortex-A9
- arm-linux-gnueabihf
- GNU Make
An end-to-end OpenCL acceleration platform on the Terasic DE10-Nano, where a host application on the ARM Cortex-A9 dispatches compute kernels into the Cyclone V fabric. The work spans the whole stack — Quartus hardware, the MMD layer and device driver, the board support package, and the host code — kept in clean separation.
- 01
Full-stack board bring-up
Quartus hardware and Qsys system integration, the MMD implementation and ARM device driver, the OpenCL board support package, and the host application — each in its own layer with an explicit boundary between them.
- 02
Host-to-fabric dispatch over OpenCL
The ARM host enumerates the FPGA as an OpenCL device through the BSP and MMD library, then queues kernels onto the Cyclone V fabric like any other accelerator.
- 03
Two demonstration kernels
Vector addition establishes the dispatch path end to end, then a 3×3 image convolution exercises a real signal-processing workload with memory access patterns that matter.
- 04
Cross-compiled and reproducible
Host code builds with the ARM hard-float toolchain under GNU Make, and prebuilt .aocx device binaries and FPGA artifacts ship with the repo so the platform can be validated without a full toolchain install.
