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Design & Verification2026

APB UART Master Core Verification

A two-agent UVM environment closing 100% functional coverage on a 16550-compatible core

Verification environment built on a forked RTL core

  • SystemVerilog
  • UVM 1.2
  • APB
  • UART 16550
  • QuestaSim
  • VCS
  • SVA
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A UVM environment that verifies an APB-based UART master core by instantiating two cores and wiring them to talk to each other, so transmit and receive are checked against real traffic rather than a model. Two APB agents drive the pair, a central scoreboard validates end to end, and assertions police APB protocol compliance throughout.

UVM testbench architecture with two APB agents and a shared scoreboard
Two agents, two cores, one scoreboard.
100%
Functional coverage
9
Test scenarios
2
APB agents
0
Assertion failures
  1. 01

    Two DUVs, one closed loop

    Rather than verify a transmitter against a predicted bitstream, two UART cores face each other. Whatever one sends the other must receive, which turns serialization, framing and timing into an end-to-end check.

  2. 02

    Per-agent drivers, monitors and sequencers

    Each APB agent carries its own driver, monitor and sequencer, feeding a shared scoreboard so traffic from either side is checked against the same reference.

  3. 03

    Error injection across nine scenarios

    Parity errors, break conditions, buffer overrun, framing errors, transmit register states and timeouts — each with a dedicated test rather than being folded into a random soak.

  4. 04

    Assertion-backed protocol compliance

    SystemVerilog assertions check APB transaction legality continuously, so a protocol violation fails at the moment it happens rather than as a downstream data mismatch.

Functional coverage report at 100%
Coverage closure across all nine scenarios.
Waveform of an APB transaction and the resulting UART frame
APB write to serial frame, captured end to end.